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ICS409
PC PERIPHERAL CLOCK
Description
The ICS409 is a cost-effective clock synthesizer developed to optimize component count for PC peripheral applications. The device supports a common, low cost 14.31818 MHz crystal using an on-chip crystal oscillator. The device locks all output frequencies to enhance system performance. By supporting common PC peripheral interface frequencies including dual 25 MHz and 40/80 MHz frequencies the clock lowers chip count enhancing system cost and reliability. The ICS409 utilizes a low pin count 8-pin SOIC package to optimize board space. ICS is a leader in low jitter and power consumer application clock sources. These devices are capable of supporting CCD, video, audio, USB, CPU, and other peripherals.
Features
* * * * * * * * *
Pin compatible with FS6286-01 Low operating voltage of 3.3V On-chip oscillator supports 14.31818 MHz crystal Fixed dual 25 MHz clocks for Ethernet 40/80 MHz selected on rising edge of OE/LAT pin Power consumption of 15 mA (typ) Duty cycle of 45 to 55% Packaged in 8-pin SOIC Available in Pb (lead) free package
Block Diagram
VDD
25M X1 1 4 .3 1 8 1 8 M H z F u n d a m e n ta l C ry s ta l X2 C ry s ta l O s c illa to r
PLL
4 0 /8 0 M
25M
GND
O E /L A T
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ICS409 PC PERIPHERAL CLOCK
Pin Assignment
OE /LAT X1 X2 VDD
40/80M Frequency Selection
8 7 6 5
25M 25M GND 40/80M
1 2 3 4
40/80M (pin 5)
0 1
Output Freq
40M 80M
Note: See below for operations of frequency selection
8 Pin (150 mil) S OIC
Pin Descriptions
Pin Number
1 2 3 4 5 6 7 8
Pin Name
OE/LAT X1 X2 VDD 40/80M GND 25M 25M
Pin Type
Input Input Input Power Input/ Output Power Output Output
Pin Description
Disables or latches 40/80 MHz output dependant on pin 5 level. Crystal connection. Connect to 14.31818 MHz parallel mode crystal. Crystal connection. Connect to 14.31818 MHz parallel mode crystal. Connect to voltage supply. 40M or 80M selection pin and clock output (see below for operation). Tri-state when OE/LAT is low. Connect to ground. 25 MHz clock output. 25 MHz clock output.
External Components
Series Termination Resistor
Clock output traces over one inch should use series termination. To series terminate a 50 trace (a commonly used trace impedance), place a 33 resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20.
Crystal Load Capacitors
The device crystal connections should include pads for small capacitors from X1 to ground and from X2 to ground. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. Because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short PCB traces (and no vias) been the crystal and device. Crystal capacitors must be connected from each of the pins X1 and X1 to ground. The value (in pF) of these crystal caps should equal (CL -6pF)*2. In this equation, CL= crystal load capacitance in pF. Example: For a crystal with a 15 pF
Decoupling Capacitor
As with any high performance mixed-signal IC, the ICS409 must be isolated from system power supply noise to perform optimally. A decoupling capacitor of 0.01F must be connected between VDD and the PCB ground plane.
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ICS409 PC PERIPHERAL CLOCK
load capacitance, each crystal capacitor would be 18 pF [(15-6) x 2] = 18.
spaces, instead they should be separated and away from other traces. 3) To minimize EMI the 33 series termination resistor, if needed, should be placed close to the clock output. 4) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. Other signal traces should be routed away from the ICS409. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device.
PCB Layout Recommendations
For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) The 0.01F decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. 2) The external crystal should be mounted just next to the device with short traces. The X1 and X2 traces should not be routed next to each other with minimum
Selection of 40M/80M Clock
The 40/80M output clock is selected by a soft pull-up or pull-down on 40/80M pin (pin 5). A rising edge on OE/LAT latches in the high or low level on pin 5 which starts the appropriate frequency.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS409. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD All Inputs and Outputs Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature 7V
Rating
-0.5 V to VDD+0.5 V 0 to +70 C -65 to +150 C 175 C 260 C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature Power Supply Voltage (measured in respect to GND)
Min.
0 +3.00
Typ.
-
Max.
+70 +3.60
Units
C V
DC Electrical CharacteristicsDC Electrical Characteristics (continued)
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ICS409 PC PERIPHERAL CLOCK VDD=3.3V 10%
Parameter
Operating Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Operating Supply Current Short Circuit Current Suggested Pull-up or Pull-down resistor on pin 5
Symbol
VDD VIH VIL VOH VOL IDD IOS R
Conditions
Min.
3.0 Vdd-0.5
Typ.
Max.
3.6 0.5
Units
V V V V V mA mA k
IOH = -25 mA IOL = 25 mA No load Each output
2.4 0.8 15 50 10
AC Electrical Characteristics
VDD = 3.3V 10%, Ambient Temperature 0 to +70x C
Parameter
Input Frequency Output Rise Time Output Fall Time Output Clock Duty Cycle Absolute Jitter, Short Term tOR tOF 0.8 to 2.0 V, CL=15 pF 2.0 to 0.8 V, CL=15 pF at VDD/2 variation from mean 45
Symbol
Conditions
Min.
Typ.
14.318 0.8 0.6 50
Max. Units
MHz ns ns 55 % ps
250
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ICS409 PC PERIPHERAL CLOCK
Package Outline and Package Dimensions (8 pin SOIC, 150 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters Symbol Min Max Inches Min Max
A A1 B C D E
In d e x A re a
1.35 1.10 0.33 0.19 4.80 3.80 5.80 0.25 0.40 0
1.75 0.25 0.51 0.25 5.00 4.00 6.20 0.50 1.27 8
0.0532 0.0040 0.013 0.0075 .1890 0.1497 0.2284 0.010 0.016 0
0.0688 0.0098 0.020 0.0098 .1968 0.1574 0.2440 0.020 0.050 8
e
E H
1.27 Basic
0.050 Basic
H h L a
P in 1
D
h x 450
A Q e b c
Ordering Information
Part / Order Number
ICS409M ICS409MT ICS409MLF ICS409MLFT
Marking
ICS409 ICS409 409MLF 409MLF
Shipping Packaging
Tubes Tape and Reel Tubes Tape and Reel
Package
8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC
Temperature
0 to 70 C 0 to 70 C 0 to 70 C 0 to 70 C
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
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